The present invention relates generally to integrated circuit (IC) packages. More particularly, the invention relates to improvements in wafer level IC packaging.
The packaging of ICs is an important aspect of manufacturing IC devices. Significant issues in manufacturing IC packages are often cost and device reliability. Costs in IC packaging include bill-of-materials and cost of assembly. In addition, the percentage of devices that pass minimum requirements, or production yield, is an important cost containment measure. Efforts have continually been made to reduce packaging cost. One relatively recently developed package is the chip-scale xe2x80x9cShellOPxe2x80x9d type packaging technology developed by Shellcase Ltd. of Israel. A cross-sectional view of a typical ShellOP package is shown by way of example in FIG. 1.
The ShellOP package is a wafer level packaging technology where substantially all of the packaging process occurs on the IC wafer directly, instead of being a separate process after the wafer is diced. Wafer level packaging enables making chip-scale IC packages with very accurate mechanical alignment and materials processing. IC package 100 is an optically active device based on the ShellOP packaging design. The packaging process employs standard wafer processing techniques such as grinding, photolithography, etching, metal deposition, plating, and dicing. Unlike many packaging methods, the Shellcase process requires no lead frames, or wire bonding. The optical package comprises semiconductor bulk 102, which is held in placed in between a top glass plate 104 and a lower glass plate 106 by epoxy 116 and 118, respectively. Inverted external leads 107 are electrically connected to die terminals 206 by trace contacts 110 at junctions 112. Junction 112 is sometimes referred to as a T-junction, and contact 110 as a T-junction contact. External leads 107 are coated with a protective solder-mask 111. Solder-mask 111 is a dielectric material that electrically isolates leads 107 from external contact, and protects the lead surface against corrosion. Contacts 114 are attached to the bottom end of leads 107, and are suitable for printed circuit board (PCB) mounting by known methods. Contacts 114 may be formed by known methods such as solder-balls or plating, and may be suitably shaped for PCB mounted.
To better appreciate the important steps in forming IC package 100, the wafer level packaging process will herein be briefly described. Usually, a semiconductor wafer has a large number of isolated device areas that are later individually packaged for use. FIG. 2a illustrates a diagrammatic cross-sectional view of the initial stage of the ShellOP wafer level packaging process for three representative device areas. The ShellOP packaging process starts with processed wafer 202. Wafer 202 has a multiplicity of device areas that are each defined between dice saw lines 204. Saw lines 204, also referred to as the xe2x80x9csaw streetxe2x80x9d, define where the wafer will be cut, or diced, into singulated devices. Each device area has passivation layer 208 and a multiplicity of metal die terminals 206 formed on the wafer and appropriately connected to circuitry in the die. Usually, passivation layer 208 is applied over the active surface area of the wafer, leaving contacts 206 exposed. Passivation layer 208 prevents materials subsequently deposited over the wafer surface from contaminating circuits in the die. A benzocyclobutene (BCB) layer 210 is deposited onto passivation layer 208. An aluminum interconnect layer 212 is patterned over BCB layer 210, wherein the patterned traces electrically couple die terminals 206 to later formed leads for external device connection. The top protective structure is formed, as illustrated in FIG. 2b, by attaching glass cover 104 onto the wafer""s topside via optical clear epoxy 116. The structural rigidity provided by glass cover 104 permits wafer 202 to be thinned by material removal process 214, which uniformly removes bottom-side wafer material until a predetermined wafer thickness is achieved.
As shown in FIG. 2c, the wafer is then etched from the bottom along saw-streets 204 by etching process 216, isolating semiconductor bulk device regions 102. For example, etching process 216 can be a selective silicon etching method. Passivation layer 208 is an etch-stop to etching process 216, whereby a multiplicity of trench-like structures aligned with saw-streets 204 are created. As illustrated in FIG. 2d, lower glass cover 106 is adhesively attached to the wafer""s bottom surface via epoxy resin 118, forming the IC package""s lower protective structure. Epoxy resin 118 fills all the etched trenches previously created.
To begin the process of lead formation, wafer assembly 200 is notched from the bottom side along saw-streets 204, the notch extending through trace layer 212 and up to top glass cover 104, whereby the lower surface of the top glass cover 104 is cut into. The resulting structure is shown in FIG. 2e. Importantly, the notches cut into the wafer assembly cut through traces in trace layer 212 that extended over the saw-street, thereby exposing a cross-sectional surface of T-junction contacts 110 at T-junction 112. T-junction contacts 110 are simply traces that are cut in the saw-street that will be connected at T-junction 112 to later formed leads. It should be noted that the exposed surfaces of T-junction contacts 110 are prone to corrosion during the manufacturing process and must be cleaned before subsequently depositing external leads. The cleaning procedure (not shown) is referred to as an anti corrosion treatment (ACT). Leads 107 are formed, as shown in FIG. 2f, by depositing aluminum onto the exposed surface of the notches previously cut into bottom-side saw-streets, thereby making physical, non-metallurgical, contact between leads 107 and the exposed ACT cleaned surface of T-junction contact 110 at T-junction 112. Leads 107 are further deposited below bottom glass cover 106, terminating at locations where PCB contacts will be formed thereon.
FIG. 2g illustrates a cross-section of the pre-singulated wafer assembly, where to avoid short-circuits from occurring, dielectric 319 is applied onto the exposed surface of leads 107, leaving uncovered bottom-side areas where contacts 114 are attached for PCB mounting. The multiplicity of device areas are thereafter singulated into individual IC packages by cutting through saw-streets 204, thereby making the completed IC package 100 illustrated in FIG. 1.
Although the foregoing wafer-level packaging process generally works well, there are continuing efforts to improve the package reliability and yield. It would also be desirable if these process improvements are also applicable to some other package designs.
To achieve the foregoing and other objects of the invention, a few improvements that are generally applicable to ShellOP style wafer level packaging processes are described. Generally, in Shellcase style packaging, traces are patterned on the top surface of a wafer. A top substrate is thereafter adhered directly or indirectly to a top surface of the wafer over the trace layer. Trenches are formed between the dice from a backside of the wafer and a bottom substrate is adhered directly or indirectly to a bottom surface of the trenched wafer. The backside of the resulting sandwiched wafer structure is then notched along the dice lines such that the notches cut through the bottom substrate and the traces thereby exposing portions of the traces. Conductors are then formed that extend into the notched surface of the sandwiched wafer structure. The conductors are arranged to contact, but not metallurgically bond with associated traces.
In one aspect of the invention, the conductors are formed from first and second conductor layers. In some embodiments, one of the conductors layers and the traces are both formed from aluminum and the second conductor layer is formed from a material that improves the adhesion of the conductors to the traces. By way of example, titanium and titanium based alloys such as titanium nitride (TiN) work well as the first conductor layer.
In another aspect of the invention, the conductors are plated with a conductive material that does not readily significantly oxidize when exposed to ambient air. The conductors are also patterned such that the conductors are not exposed during the dicing operation. This arrangement is particularly useful when the conductors are formed at least partially from aluminum (or other metals that oxidize in ambient air). In yet another aspect of the invention, BCB is not used under the trace layer in regions near the T-junction so that the resulting package does not have any exposed BCB/trace junctions. In some embodiments, no BCB layer whatsoever is applied during packaging. In other embodiments, prior to the formation of the trace layer, a BCB layer is formed over a top surface of the wafer. However, the BCB layer is patterned to avoid dice line areas that will later be trenched or notched
In other aspects of the invention, improved integrated circuit package structures are described. In various aspects, a shell case type package is provided having a die that is sandwiched by a pair of substrates. Conductive traces are formed over the top surface of the die and conductors are formed along the sides of the die. Typically, the conductors extend along the bottom surface of the lower substrate. The conductors contact but are not metallurgically bonded to their respective associated traces.
In another package aspect of the invention, the conductors are formed from multiple layers in order to improve the adhesion of the conductors to the traces. By way of example, in embodiments where the traces and the second conductive layer are formed from aluminum, the first conductive layer may be formed from a variety of materials including titanium and titanium based alloys. In various embodiments, the substrate layers are formed from glass. An adhesive material such as epoxy is used to adhere the glass layers to the die. With this arrangement, the portions of the conductors that extend along the sides of the die directly contact the adhesive and not the sides of the die itself.
In other aspects of the invention, improved intermediate structures are provided which are useful in wafer based packaging of integrated circuits.